This invention relates to a parallel-toserial converter, and more specifically, to a parallel-to-serial converter for multiplexing a plurality of parallel input data into a serial data.
Recently, transmission apparatus with high speed operation has been achieved. The current transmission rate in such an optical communication system has reached the order of gigabit/second.
To obtain such a high speed transmission rate, it is conventional practice to use multiplex techniques. Since a parallel-to-serial conversion is considered a simple method of multiplexing, a parallel-to-serial converter is often used for a multiplexer operated under high speed.
Moreover, it has also been known to employ a synchronous multiplexing network, such as Integrated Services for Digital Network ("ISDN") and Synchronous Optical Network ("SONET"), to easily connect the communication systems. The basic transmission rate is selected to several tens of megabit/second and a multiplexing pulse code modulation ("PCM") hierarchy is set to an integer multiple of this basic transmission rate.
In this synchronous multiplexing system, each network and each transmission line are synchronized with each other in order to easily connect one network to another and to form a simple and less costly multiplexer by parallel-toserial conversion.
Therefore, a parallel-to-serial converter is now frequently employed for a multiplexer to realize a stable high speed data transmission yet less costly system.
As transmission speed has increased, however, converting a plurality of parallel input data into a serial data adversely reduces the phase margin in the parallel-to-serial converter, in view of a phase relation between a clock signal deciding an output timing of each of the parallel input data and the parallel input data themselves. Accordingly, in such a high speed operation, a rising time and falling time of a waveform of an input data, and a set up time and holding time of circuit elements in a parallel-to-serial converter cannot be neglected so that the phase margin of input data is occupied by the above rising and falling time and the set up and holding time.
When the phase margin becomes reduced, it is difficult to realize a stable operation and a higher speed operation of a parallel-to-serial converter.